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1 LTC1343 software-selectable multiprotocol transceiver n software-selectable transceiver supports: rs232, rs449, eia-530, eia-530-a, v.35, v.36, x.21 n net1 and net2 compliant n software-selectable cable termination using the ltc1344 n 4-driver/4-receiver configuration provides a complete 2-chip dte or dce port n operates from single 5v supply n internal echoed clock and loop-back logic the ltc ? 1343 is a 4-driver/4-receiver multiprotocol trans- ceiver that operates from a single 5v supply. two LTC1343s form the core of a complete software-selectable dte or dce interface port that supports the rs232, rs449, eia-530, eia-530-a, v.35, v.36 or x.21 protocols. cable termination may be implemented using the ltc1344 software-selectable cable termination chip or by using existing discrete designs. the LTC1343 runs from a single 5v supply using an internal charge pump that requires only five space saving surface mount capacitors. the mode pins are latched internally to allow sharing of the select lines between multiple interface ports. software-selectable echoed clock and loop-back modes help eliminate the need for external glue logic between the serial controller and line transceiver. the part features a flow- through architecture to simplify emi shielding and is available in the 44-lead ssop surface mount package. dte multiprotocol serial interface with db-25 connector , ltc and lt are registered trademarks of linear technology corporation. n data networking n csu and dsu n data routers d2 LTC1343 rts dtr dsr dcd cts rl d1 d3 d4 r1 r3 r4 r2 d2 LTC1343 ll txd scte txc rxc rxd tm ll a (141) txd a (103) txd b scte a (113) scte b rxc a (115) rxc b rxd a (104) rxd b rts a (105) rts b dtr a (108) dtr b cts a (106) cts b tm a (142) sgnd (102) shield (101) 18 2 14 24 11 15 12 17 9 3 1 4 19 20 23 6 22 8 10 5 13 21 7 16 25 1343 ta01 db-25 connector ltc1344 d1 d3 d4 r1 r3 r4 r2 txc a (114) txc b rl a (140) dcd a (109) dcd b dsr a (107) dsr b features descriptio u applicatio s u typical applicatio u
2 LTC1343 absolute m axi m u m ratings w ww u package/order i n for m atio n w u u order part number t jmax = 150 c, q ja = 65 c/ w consult factory for military grade parts. (note 1) supply voltage ....................................................... 6.5v input voltage transmitters ........................... C 0.3v to (v cc + 0.3v) receivers ............................................... C 18v to 18v logic pins .............................. C 0.3v to (v cc + 0.3v) output voltage transmitters ................. (v ee C 0.3v) to (v dd + 0.3v) receivers ................................ C 0.3v to (v cc + 0.3v) logic pins .............................. C 0.3v to (v cc + 0.3v) v ee ........................................................ C 10v to 0.3v v dd ....................................................... C 0.3v to 10v short-circuit duration transmitter output ..................................... indefinite receiver output .......................................... indefinite v ee .................................................................. 30 sec operating temperature range LTC1343c .............................................. 0 c to 70 c LTC1343i ........................................... C 40 c to 85 c storage temperature range ................ C 65 c to 150 c lead temperature (soldering, 10 sec)................. 300 c 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 top view gw package 44-lead plastic ssop 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 v dd c1 + pwrv cc c1 d1 d2 d3 v cc d4 d4en invert r1en r1o r2o r3o r4o m0 m1 m2 ctrl/clk dce/dte latch c2 + c2 v ee pgnd gnd d1 a d2 a d2 b d3 a d3 b d4 a d4 b r1 a r1 b r2 a r2 b r3 a r3 b r4 a 423 set ec lb d2 d3 d1 d4 r1 r2 r3 r4 charge pump LTC1343cgw LTC1343igw electrical characteristics symbol parameter conditions min typ max units supplies i cc v cc supply current (dce mode, v.10 mode, no load 12 ma all digital pins = gnd or v cc ) v.10 mode, full load l 80 150 ma rs530, rs530-a, x.21 modes, no load 80 ma rs530, rs530-a, x.21 modes, full load l 160 200 ma v.35 mode, no load 20 ma v.35 mode, full load l 115 160 ma v.28 mode, no load 20 ma v.28 mode, full load l 30 90 ma no-cable mode l 0.05 1 ma p d internal power dissipation (dce mode, v.10 mode, full load 400 mw all digital pins = gnd or v cc ) rs530, rs530-a, x.21 modes, full load 680 mw v.35 mode, full load 500 mw v.28 mode, full load 150 mw v + positive charge pump output voltage any mode, no load l 8.5 9.1 v v.28 mode, with load l 8.0 7.0 v v C negative charge pump output voltage v.28 mode, full load l C 7.8 C 8.4 v v.35 mode, full load l C 5.8 C 6.7 v C40 c t a 85 c l C 5.5 v v.10, rs530, rs530a, x.21 modes, full load l C 5.0 C 6.1 v C40 c t a 85 c l C 4.8 v the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = 5v (notes 2, 3)
3 LTC1343 electrical characteristics the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = 5v (notes 2, 3) symbol parameter conditions min typ max units t r supply rise time no-cable mode or power-up to turn on 2 ms logic inputs and outputs v ih logic input high voltage l 2v v il logic input low voltage l 0.8 v i in logic input current l 10 m a v oh output high voltage i o = C 4ma l 3 4.5 v v ol output low voltage i o = 4ma l 0.3 0.8 v i osr output short-circuit current 0v v o v cc , 0 c t a 70 c l C60 60 ma 0v v o v cc , C 40 c t a 85 c l C70 70 ma i ozr three-state output current m0 = m1 = m2 = v cc , 0v v o v cc 1 m a v.11 driver v od differential output voltage open circuit, r l = 1.95k l 6v r l = 50 w (figure 1), l 2v v od at 50 w > 1/2 v od at r l = 1.95k d v od change in magnitude of differential r l = 50 w (figure 1) l 0.2 v output voltage v oc common mode output voltage r l = 50 w (figure 1) l 3.0 v d v oc change in magnitude of common mode r l = 50 w (figure 1) l 0.2 v output voltage i ss short-circuit current C 0.25v v o 0.25v, power off or 150 ma no-cable mode or driver disabled i oz output leakage current C 0.25v v o 0.25v, power off or l 0.01 100 m a no-cable mode or driver disabled t r , t f rise or fall time (figures 2, 6) l 41325 ns t plh input to output (figures 2, 6), 0 c t a 70 c l 25 55 80 ns (figures 2, 6), C 40 c t a 85 c l 25 55 90 ns t phl input to output (figures 2, 6), 0 c t a 70 c l 25 55 80 ns (figures 2, 6), C 40 c t a 85 c l 25 55 90 ns d t input to output difference, ? t plh C t phl ? (figures 2, 6), 0 c t a 70 c l 0317 ns (figures 2, 6), C 40 c t a 85 c l 0325 ns t skew output to output skew (figures 2, 6) 3 ns v.11 receiver v th input threshold voltage C 7v v cm 7v, 0 c t a 70 c l C 0.2 0.2 v C7v v cm 7v, C 40 c t a 85 c l C 0.3 0.3 v d v th input hysteresis C 7v v cm 7v, 0 c t a 70 c l 15 40 mv C7v v cm 7v, C 40 c t a 85 c l 60 mv i in input current (a, b) C 10v v a, b 10v l 0.50 ma r in input impedance C 10v v a, b 10v l 20 32 k w t r , t f rise or fall time (figures 2, 7) 15 ns t plh input to output (figures 2, 7), ctrl = gnd, 0 c t a 70 c l 35 80 115 ns ctrl = v cc , 0 c t a 70 c 400 ns (figures 2, 7), ctrl = gnd, C 40 c t a 85 c l 25 80 130 ns ctrl = v cc , C 40 c t a 85 c 400 ns
4 LTC1343 electrical characteristics the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = 5v (notes 2, 3) symbol parameter conditions min typ max units t phl input to output (figures 2, 7), ctrl = gnd, 0 c t a 70 c l 35 80 115 ns ctrl = v cc , 0 c t a 70 c 400 ns (figures 2, 7), ctrl = gnd, C40 c t a 85 c l 25 80 130 ns ctrl = v cc , C40 c t a 85 c 400 ns d t input to output difference, ? t plh C t phl ? (figures 2, 7), 0 c t a 70 c l 0517 ns (figures 2, 7), C40 c t a 85 c l 0525 ns v.35 driver v od differential output voltage open circuit 6.0 v with load, C 4.0v v cm = 4.0v (figure 3) l 0.44 0.55 0.66 v i oh transmitter output high current v a, b = 0v l C 12.6 C 11 C 9.4 ma i ol transmitter output low current v a, b = 0v l 9.4 11 12.6 ma i oz transmitter output leakage current C 0.25v v a, b 0.25v l 0.01 100 m a t r , t f rise or fall time (figures 3, 6) 5 ns t plh input to output (figures 3, 6), 0 c t a 70 c l 25 45 75 ns (figures 3, 6), C40 c t a 85 c l 25 45 90 ns t phl input to output (figures 3, 6), 0 c t a 70 c l 25 45 75 ns (figures 3, 6), C40 c t a 85 c l 25 45 90 ns d t input to output difference, ? t plh C t phl ? (figures 3, 6), 0 c t a 70 c l 0517 ns (figures 3, 6), C40 c t a 85 c l 0525 ns t skew output to output skew (figures 3, 6) 4 ns v.35 receiver v th differential receiver input C 2v (v a + v b )/2 2v (figure 3) l C 0.2 0.2 v threshold voltage d v th receiver input hysteresis C 2v (v a + v b )/2 2v (figure 3) l 11 40 mv i in receiver input current (a, b) C 10v v a, b 10v l 0.50 ma r in receiver input impedance C 10v v a, b 10v l 20 32 k w t r , t f rise or fall time (figures 3, 7) 15 ns t plh input to output (figures 3, 7), 0 c t a 70 c l 80 115 ns (figures 3, 7), C40 c t a 85 c l 80 130 ns t phl input to output (figures 3, 7), 0 c t a 70 c l 100 115 ns (figures 3, 7), C40 c t a 85 c l 100 130 ns d t input to output difference, ? t plh C t phl ? (figures 3, 7), 0 c t a 70 c l 417 ns (figures 3, 7), C40 c t a 85 c l 425 ns v.10 driver v o output voltage open circuit, r l = 3.9k 4.0 6.0 v r l = 450 w (figure 4) 3.6 v v o at 450 w > 0.9 v o at r l = 3.9k driver 1 only i ss short-circuit current v o = gnd; eia-530, x.21, eia-530-a modes 150 ma i oz output leakage current C 0.25v v o 0.25v, power off or l 0.1 100 m a no-cable mode or driver disabled t r , t f rise or fall time (figures 4, 8), r l = 450 w , c l = 100pf r 423set = 100k 4 m s t plh input to output (figures 4, 8), r l = 450 w , c l = 100pf r 423set = 100k 8 m s t phl input to output (figures 4, 8), r l = 450 w , c l = 100pf r 423set = 100k 8 m s
5 LTC1343 v dd (pin 1): generated positive supply voltage for rs232. connect a 1 m f capacitor to ground. c1 + (pin 2): capacitor c1 positive terminal. connect a 1 m f capacitor between c1 + and c1 C . pwrv cc (pin 3): positive supply for the charge pump. 4.75v pwrv cc 5.25v. tie to v cc (pin 8) and bypass with a 1 m f capacitor to ground. pi n fu n ctio n s uuu c1 C (pin 4): capacitor c1 negative terminal. d1 (pin 5): ttl level driver 1 input. d2 (pin 6): ttl level driver 2 input. d3 (pin 7): ttl level driver 3 input. becomes a cmos level output when the chip is in the echoed clock mode (ec = 0v). note 1: absolute maximum ratings are those beyond which the safety of a device may be impaired. note 2: all currents into device pins are positive; all currents out of device are negative. all voltages are referenced to device ground unless otherwise specified. note 3: all typicals are given for v cc = 5v, c1 = c2 = c vcc = c vdd = 1 m f, c vee = 3.3 m f tantalum capacitors and t a = 25 c. electrical characteristics the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = 5v (notes 2, 3) symbol parameter conditions min typ max units v.10 receiver v th receiver input threshold voltage 0 c t a 70 c l C 0.2 0.2 v C7v v cm 7v, C 40 c t a 85 c l C 0.3 0.3 v d v th receiver input hysteresis l 11 50 mv i in receiver input current C 10v v a 10v l 0.50 ma r in receiver input impedance C 10v v a 10v l 20 30 k w t r , t f rise or fall time (figures 5, 9) 15 ns t plh input to output (figures 5, 9) 350 ns t phl input to output (figures 5, 9) 350 ns v.28 driver v o output voltage open circuit 10 v r l = 3k (figure 4) l 5 7.6 v i ss short-circuit current v o = gnd l 150 ma i oz output leakage current C 0.25v v o 0.25v, power off or l 0.01 100 m a no-cable mode or driver disabled sr slew rate (figures 4, 8), r l = 3k, c l = 2500pf l 4.0 30.0 v/ m s t plh input to output (figures 4, 8), r l = 3k, c l = 2500pf l 1.6 2.5 m s t phl input to output (figures 4, 8), r l = 3k, c l = 2500pf l 1.6 2.5 m s v.28 receiver v thl input low threshold voltage l 1.4 0.8 v v tlh input high threshold voltage l 2.0 1.4 v d v th receiver input hysteresis l 0.1 0.4 1.0 v r in receiver input impedance C 15v v a 15v l 357 k w t r , t f rise or fall time (figures 5, 9) 15 ns t plh input to output (figures 5, 9), ctrl = 0v 110 ns ctrl = v cc l 330 800 ns t phl input to output (figures 5, 9), ctrl = 0v 170 ns ctrl = v cc l 480 800 ns
6 LTC1343 pi n fu n ctio n s uuu respective input buffers. the data latch allows the logic lines to be shared between multiple i/o ports. lb (pin 23): ttl level loop-back select input. when low the chip enters the loop-back configuration and is config- ured for normal operation when lb is high. the data on lb is latched when latch is high. ec (pin 24): ttl level echoed clock select input. when low the part enters the echoed clock configuration and is configured for normal operation when ec is high. the data on ec is latched when latch is high. 423 set (pin 25): analog input pin for the rs423 driver output rise and fall time set resistor. connect the resistor from the pin to ground. r4 a (pin 26): receiver 4 inverting input. r3 b (pin 27): receiver 3 noninverting input. r3 a (pin 28): receiver 3 inverting input. r2 b (pin 29): receiver 2 noninverting input. r2 a (pin 30): receiver 2 inverting input. r1 b (pin 31): receiver 1 noninverting input. r1 a (pin 32): receiver 1 inverting input. d4 b (pin 33): driver 4 noninverting output. d4 a (pin 34): driver 4 inverting output. d3 b (pin 35): driver 3 noninverting output. d3 a (pin 36): driver 3 inverting output. d2 b (pin 37): driver 2 noninverting output. d2 a (pin 38): driver 2 inverting output. d1 a (pin 39): driver 1 inverting output. gnd (pin 40): signal ground. connect to pgnd (pin 41). pgnd (pin 41): charge pump power ground. connect to the gnd (pin 40). v ee (pin 42): generated negative supply voltage. connect a 3.3 m f capacitor to ground. c2 C (pin 43): capacitor c2 negative terminal. connect a 1 m f capacitor between c2 + and c2 C . c2 + (pin 44): capacitor c2 positive terminal. connect a 1 m f capacitor between c2 + and c2 C . v cc (pin 8): positive supply for the transceivers. 4.75v v cc 5.25v. tie to pwrv cc (pin 3). d4 (pin 9): ttl level driver 4 input. d4en (pin 10): ttl level enable input for driver 4. when high, driver 4 outputs are enabled. when low, driver 4 outputs are forced into a high impedance state. d4en is not affected by the latch pin. invert (pin 11): ttl level signal invert input. when high, an extra inverter will be added to the driver 4 and receiver 1 signal path. the data stream will change polar- ity, i.e., a 1 becomes 0 and a 0 becomes a 1. when the pin is low the data flows through with no polarity change. invert is not affected by the latch pin. r1en (pin 12): logic level enable input for receiver 1. when low, receiver 1 output is enabled. when high, receiver 1 output is forced into a high impedance state. r1o (pin 13): cmos level receiver 1 output. r2o (pin 14): cmos level receiver 2 output. r3o (pin 15): cmos level receiver 3 output. r4o (pin 16): cmos level receiver 4 output. m0 (pin 17): ttl level mode select input 0. the data on m0 is latched when latch is high. m1 (pin 18): ttl level mode select input 1. the data on m1 is latched when latch is high. m2 (pin 19): ttl level mode select input 2. the data on m2 is latched when latch is high. ctrl/clk (pin 20): ttl level mode select input. when the pin is low the chip will be configured for clock and data signals. when the pin is high the chip will be configured for control signals. the data on ctrl/clk is latched when latch is high. dce/dte (pin 21): ttl level mode select input. when high, the dce mode is selected. when low the dte mode is selected. the data on dce/dte is latched when latch is high. latch (pin 22): ttl level logic signal latch input. when low the input buffers on m0, m1, m2, ctrl/clk, dce/ dte, lb and ec are transparent. when latch is pulled high the data on the logic pins is latched into their
7 LTC1343 test circuits figure 1. rs422 driver test circuit figure 2. rs422 driver/receiver ac test circuit figure 4. v.10/v.28 driver test circuit figure 5. v.10/v.28 receiver test circuit figure 3. v.35 driver/receiver test circuit ode selectio w u LTC1343 mode name m2 m1 m0 ctrl/clk d1 d2 d3 d4 r1 r2 r3 r4 v.10, rs423 0 0 0 x v.10 v.10 v.10 v.10 v.10 v.10 v.10 v.10 eia-530-a clock and data 0 0 1 0 v.10 v.11 v.11 v.11 v.11 v.11 v.11 v.10 eia-530-a control 0 0 1 1 v.10 v.11 v.10 v.11 v.11 v.10 v.11 v.10 reserved 0 1 0 x v.10 v.11 v.11 v.11 v.11 v.11 v.11 v.10 x.21 0 1 1 x v.10 v.11 v.11 v.11 v.11 v.11 v.11 v.10 v.35 clock and data 1 0 0 0 v.28 v.35 v.35 v.35 v.35 v.35 v.35 v.28 v.35 control 1 0 0 1 v.28 v.28 v.28 v.28 v.28 v.28 v.28 v.28 eia-530, rs449, v.36 1 0 1 x v.10 v.11 v.11 v.11 v.11 v.11 v.11 v.10 v.28, rs232 1 1 0 x v.28 v.28 v.28 v.28 v.28 v.28 v.28 v.28 no cable 1 1 1 x z z z z z z z z a b 1343 f01 v od v oc r l 50 w r l 50 w a b a r b 1343 f02 r l 100 w c l 100pf c l 100pf 15pf a b d a b 1343 f03 r v od v cm 50 w 125 w 125 w 50 w 50 w 50 w 15pf a d 1343 f04 r l c l a d 1343 f04 15pf r a
8 LTC1343 switchi g ti e wavefor s uw w figure 6. v.11, v.35 driver propagation delays figure 7. v.11, v.35 receiver propagation delays figure 8. v.10, v.28 driver propagation delays figure 9. v.10, v.28 receiver propagation delays 5v 1.5v 1.5v 50% 10% 90% t plh t r 0v v o v o ? o d b ?a a b t phl t skew t skew 1343 f06 1/2 v o f = 1mhz : t r 10ns : t f 10ns v diff = v(a) ?v(b) 50% 10% 90% t f v od2 ? od2 0v 1.5v 0v 1.5v t plh v oh v ol b ?a r t phl 1343 f07 f = 1mhz : t r 10ns : t f 10ns input output 3v 0v 1.5v 0v ?v 3v 1.5v 0v 3v ?v t phl t f v o ? o d a t plh t r 1343 f08 v ih v il 1.3v 0.8v 1.7v 2.4v t phl v oh v ol a r t plh 1343 f09
9 LTC1343 applicatio n s i n for m atio n wu u u software-selectable cable termination chip or by using existing discrete designs. a complete dce-to-dte interface operating in eia-530 mode is shown in figure 10. the first LTC1343 of each port is used to generate the clock and data signals along with ll (local loop-back) and tm (test mode). the second LTC1343 is used to generate the control signals along with figure 10. complete multiprotocol interface in eia-530 mode overview the LTC1343 is a 4-driver/4-receiver multiprotocol trans- ceiver that operates from a single 5v supply. two LTC1343s form the core of a complete software-selectable dte or dce interface port that supports the rs232, rs449, eia-530, eia-530-a, v.35, v.36 or x.21 protocols. cable termination may be implemented using the ltc1344 LTC1343 dce dte LTC1343 ltc1344 ltc1344 1343 f10 d1 d4 d4 d3 d2 r1 r4 103 w 103 w 103 w 103 w 103 w r3 LTC1343 d1 d4 d3 d2 r1 r4 r2 r3 ll txd scte txc rxc rxd tm ll txd scte txc rxc rxd tm serial controller r3 r2 r1 r4 d3 d2 d1 LTC1343 d4 r3 r2 r1 r4 d3 d2 d1 ll txd scte txc rxc rxd tm rl rts dtr dcd dsr cts ri rl rts dtr dcd dsr cts ri rl rts dtr dcd dsr cts ri serial controller r2
10 LTC1343 applicatio n s i n for m atio n wu u u will configure the port for dce mode when high, and dte when low. the interface protocol may be selected simply by plugging the appropriate interface cable into the connector. the mode pins are routed to the connector and are left uncon- nected (1) or wired to ground (0) in the cable as shown in figure 11. the pull-up resistors r1 through r4 will ensure a binary 1 when a pin is left unconnected and that the two LTC1343s and the ltc1344 enter the no-cable mode when the cable is removed. in the no-cable mode the LTC1343 supply current drops to less than 200 m a and all LTC1343 driver outputs and ltc1344 resistive terminations are forced into a high impedance state. note that the data latch pin, latch, is shorted to ground for all chips. the interface protocol may also be selected by the serial controller or host microprocessor as shown in figure 12. the mode selection pins m0, m1, m2 and dce/dte can be shared between multiple interface ports, while each port figure 11: single port dce/v.35 mode selection in the cable rl (remote loop-back) and ri (ring indicate). the ltc1344 cable termination chip is used only for the clock and data signals because they must support v.35 cable termination. the control signals do not need any external resistors. mode selection the interface protocol is selected using the mode select pins m0, m1, m2 and ctrl/clk (see the mode selection table). the ctrl/clk pin should be pulled high if the LTC1343 is being used to generate control signals and pulled low if used to generate clock and data signals. for example, if the port is configured as a v.35 interface, the mode selection pins should be m2 = 1, m1 = 0, m0 = 0. for the control signals, ctrl/clk = 1 and the drivers and receivers will operate in rs232 (v.28) electrical mode. for the clock and data signals, ctrl/clk = 0 and the drivers and receivers will operate in v.35 electrical mode, except for the single-ended driver and receiver which will operate in the rs232 (v.28) electrical mode. the dce/dte pin nc nc cable 1343 f11 17 18 19 21 LTC1343 LTC1343 connector 20 21 19 18 17 22 21 m2 m1 ltc1344 latch m0 (data) 23 24 1 ctrl/clk 22 (data) m0 m1 m2 dce/dte latch 20 ctrl/clk 22 dce/dte m2 m1 m0 (data) latch v cc dce/ dte r1, 10k v cc r2, 10k v cc r3, 10k v cc r4, 10k v cc
11 LTC1343 applicatio n s i n for m atio n wu u u figure 12: mode selection by the controller has a unique data latch signal which acts as a write enable. when the latch pin is low the buffers on the m0, m1, m2, ctrl/clk, dce/dte, lb and ec pins are transparent. when the latch pin is pulled high the buffers latch the data and changes on the input pins will no longer affect the chip. the mode selection may also be accomplished by using jumpers to connect the mode pins to ground or v cc . cable termination traditional implementations have included switching re- sistors with expensive relays, or requiring the user to change termination modules every time the interface standard has changed. custom cables have been used with the termination in the cable head, or separate termi- nations are built on the board and a custom cable routes the signals to the appropriate termination. switching the terminations with fets is difficult because the fets must remain off even though the signal voltage is beyond the supply voltage for the fet drivers or the power is off. using the ltc1344 along with the LTC1343 solves the cable termination switching problem. via software con- trol, the ltc1344 provides termination for the v.10 (rs423), v.11 (rs422), v.28 (rs232) and v.35 electrical protocols. v.10 (rs423) interface a typical v.10 unbalanced interface is shown in figure 13. a v.10 single-ended generator output a with ground c is connected to a differential receiver with inputs a ' con- nected to a, and input b ' connected to the signal return ground c. the receivers ground c ' is separate from the signal return. usually, no cable termination is required for v.10 interfaces, but the receiver inputs must be compliant with the impedance curve shown in figure 14. figure 14. v.10 receiver input impedance figure 13. typical v.10 interface 1343 f12 controller port #3 m0 m1 m2 dce/dte latch 1 latch 2 latch 3 m0 m1 m2 dce/dte latch port #2 m0 m1 m2 dce/dte latch port #1 m0 m1 m2 dce/dte latch connector #1 connector #2 connector #3 aa ' cb ' c ' generator balanced interconnecting cable load cable termination receiver 1343 f13 i z v z ?0v ?.25ma 3.25ma ?v 3v 10v 1343 f14
12 LTC1343 applicatio n s i n for m atio n wu u u the v.10 receiver configuration in the LTC1343 and ltc1344 is shown in figure 15. in v.10 mode switches s1 and s2 inside the ltc1344 and s3 inside the LTC1343 are turned off. switch s4 inside the LTC1343 shorts the noninverting receiver input to ground so the b input at the connector can be left floating. the cable termination is then the 30k input impedance to ground of the LTC1343 v.10 receiver. v.11 (rs422) interface a typical v.11 balanced interface is shown in figure 16. a v.11 differential generator with outputs a and b with ground c is connected to a differential receiver with ground c ' , inputs a ' connected to a, b ' connected to b. the v.11 interface has a differential termination at the receiver end that has a minimum value of 100 w . the termination resistor is optional in the v.11 specification, but for the high speed clock and data lines, the termination is required to prevent reflections from corrupting the data. the re- ceiver inputs must also be compliant with the impedance curve shown in figure 14. in v.11 mode, all switches are off except s1 inside the ltc1344 which connects a 103 w differential termination impedance to the cable as shown in figure 17. v.28 (rs232) interface a typical v.28 unbalanced interface is shown in figure 18. a. v.28 single-ended generator output a with ground c is connected to a single-ended receiver with inputs a ' con- nected to a, ground c ' connected via the signal return ground c. in v.28 mode all switches are off except s3 inside the LTC1343 which connects a 6k (r8) impedance to ground in parallel with 20k (r5) plus 10k (r6) for a combined impedance of 5k as shown in figure 19. the noninverting input is disconnected inside the LTC1343 receiver and connected to a ttl level reference voltage for a 1.4v receiver trip point. figure 17. v.11 receiver configuration figure 15. v.10 receiver configuration figure 18. typical v.28 interface figure 16. typical v.11 interface r3 124 w r5 20k ltc1344 LTC1343 receiver 1343 f15 a b a ' b ' c ' r1 51.5 w r8 6k s1 s2 s3 s4 r2 51.5 w r6 10k r7 10k gnd r4 20k aa ' b c b ' c ' generator balanced interconnecting cable load cable termination receiver 100 w min 1343 f16 r3 124 w r5 20k ltc1344 LTC1343 receiver 1343 f17 a b a ' b ' c ' r1 51.5 w r8 6k s2 s3 s4 r2 51.5 w r6 10k r7 10k gnd r4 20k s1 aa ' cc ' generator balanced interconnecting cable load cable termination receiver 1343 f18
13 LTC1343 applicatio n s i n for m atio n wu u u figure 19. v.28 receiver configuration figure 21. v.35 receiver configuration the generator differential impedance must be 50 w to 150 w and the impedance between shorted terminals (a and b) and ground c must be 150 w 15 w . for the generator termination, switches s1 and s2 are both on and the top side of the center resistor is brought out to a pin so it can be bypassed with an external capacitor to reduce common mode noise as shown in figure 22. any mismatch in the driver rise and fall times or skew in the driver propagation delays will force current through the center termination resistor to ground, causing a high frequency common mode spike on the a and b terminals. the common mode spike can cause emi problems that are reduced by capacitor c1 which shunts much of the com- mon mode energy to ground rather than down the cable. v.35 interface a typical v.35 balanced interface is shown in figure 20. a v.35 differential generator with outputs a and b with ground c is connected to a differential receiver with ground c ' , inputs a ' connected to a, b ' connected to b. the v.35 interface requires a t or delta network termination at the receiver end and the generator end. the receiver differential impedance measured at the connector must be 100 w 10 w , and the impedance between shorted termi- nals (a ' and b) and ground c ' must be 150 w 15 w . in v.35 mode, both switches s1 and s2 inside the ltc1344 are on, connecting the t network impedance as shown in figure 21. both switches in the LTC1343 are off. the 30k input impedance of the receiver is placed in parallel with the t network termination, but does not affect the overall input impedance significantly. figure 20. typical v.35 interface figure 22. v.35 driver using the ltc1344 r3 124 w r5 20k ltc1344 LTC1343 receiver 1343 f19 a b a ' b ' c ' r1 51.5 w r8 6k s2 s3 s4 r2 51.5 w r6 10k r7 10k gnd r4 20k s1 r3 124 w r5 20k ltc1344 LTC1343 receiver 1343 f21 a b a ' b ' c ' r1 51.5 w r8 6k s2 s3 s4 r2 51.5 w r6 10k r7 10k gnd r4 20k s1 a a ' b c b ' c ' generator balanced interconnecting cable load cable termination receiver 1343 f20 50 w 125 w 50 w 50 w 125 w 50 w v.35 driver a b c 51.5 w s2 on s1 on 1343 f22 51.5 w ltc1344 124 w c1 100pf
14 LTC1343 applicatio n s i n for m atio n wu u u echoed clock mode the LTC1343 contains the logic to generate the echoed clock when using a serial controller with only two clock pins. figure 23 shows the chip in both the dte and dce echoed clock in eia-530 mode. the control signals are not shown. the echoed clock configuration is selected by pulling the ec pin low. on the dte side the transmit clock txc receiver output is connected to the echoed clock, scte, driver input. the txc pin on the serial controller is configured as an input. on the dce side, the transmit clock from the serial controller is used to generate both txc and rxc. a phase inverter is placed in the txc signal path on both the dte and dce side to help correct phase problems with long cables. if the invert pin is high, the phase of the data is inverted. loop-back the LTC1343 contains logic for placing the interface into a loop-back configuration for testing. both dte and dce loop-back configurations are supported. figure 24 shows a complete dte interface in the loop-back configuration with the ec pin pulled high. the loop-back configuration is selected by pulling the lb pin low. both the line side and logic side signals are looped back. the dce loop-back configuration is shown in figure 25. if the echoed clock mode is selected by pulling ec low, d3 becomes an output and is connected to receiver 2s output r3 in dte mode as shown in figure 26. in the echoed clock dce loop-back mode, driver 4 is connected to driver 3s input d3 as shown in figure 27. figure 23. eia-530 echoed clock configuration LTC1343 dce dte LTC1343 ltc1344 ltc1344 1343 f23 d1 d4 d4 d3 d2 r1 r4 103 w 103 w 103 w 103 w 103 w r3 ll txd txc invert rxc rxd tm serial controller r3 r2 r1 r4 d3 d2 d1 ll rxd rxc invert txc txd tm serial controller r2 m0 m1 m2 ctrl/clk dce/dte lb ec latch m0 m1 m2 dce/dte latch 1 0 1 0 0 1 0 0 m0 m1 m2 ctrl/clk dce/dte lb ec latch 1 0 1 0 1 1 0 0 1 0 1 0 0 m0 m1 m2 dce/dte latch 1 0 1 1 0 ll txd scte txc rxc rxd tm
15 LTC1343 figure 24. normal dte loop-back figure 25. normal dce loop-back applicatio n s i n for m atio n wu u u LTC1343 ltc1344 1343 f24 d1 d4 d3 d2 r1 r4 103 w 103 w 103 w r3 ll txd scte txc rxc rxd tm serial controller r2 m0 m1 m2 ctrl/clk dce/dte lb ec latch m0 m1 m2 dce/dte latch 1 0 1 0 0 0 1 0 1 0 1 0 0 ll txd scte rxd LTC1343 d1 d4 d3 d2 r1 r4 r3 rl rts dtr dcd dsr cts ri r2 m0 m1 m2 ctrl/clk dce/dte lb ec latch 1 0 1 1 0 0 1 0 dcd dsr cts LTC1343 r4 d4 d3 d2 r1 d1 r3 r2 m0 m1 m2 ctrl/clk dce/dte lb ec latch LTC1343 ltc1344 1343 f25 r4 d4 d3 d2 r1 d1 103 w 103 w r3 ll txd scte txc rxc rxd tm serial controller r2 m0 m1 m2 dce/dte latch m0 m1 m2 ctrl/clk dce/dte lb ec latch 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 0 1 0 1 1 0 ll txd scte txc txc rxc rxc rxd tm tm rl rl rts rts dtr dtr dcd dsr cts ri ri rl rts dtr dcd dsr cts ri
16 LTC1343 applicatio n s i n for m atio n wu u u figure 26. echoed clock, dte loop-back figure 27. echoed clock, dce loop-back LTC1343 ltc1344 1343 f26 d1 d4 d3 d2 r1 r4 103 w 103 w 103 w r3 ll txd txc rxc rxd tm serial controller r2 m0 m1 m2 ctrl/clk dce/dte lb ec latch m0 m1 m2 dce/dte latch 1 0 1 0 0 0 0 0 1 0 1 0 0 txce txc rxc rxd LTC1343 d1 d4 d3 d2 r1 r4 r3 rl rts dtr dcd dsr cts ri r2 m0 m1 m2 ctrl/clk dce/dte lb ec latch 1 0 1 1 0 0 1 0 rts dtr dcd cts ri LTC1343 r4 d4 d3 d2 r1 d1 r3 r2 m0 m1 m2 ctrl/clk dce/dte lb ec latch LTC1343 ltc1344 1343 f27 r4 d4 d3 d2 r1 d1 103 w 103 w r3 ll rxd rxc txc txd tm serial controller r2 m0 m1 m2 dce/dte latch m0 m1 m2 ctrl/clk dce/dte lb ec latch 1 0 1 0 1 0 0 0 1 0 1 1 1 0 1 0 1 0 1 1 0 ll ll txd txd scte txc rxc rxd tm tm rl rl rts dtr dcd dsr dsr cts ri rl rts dtr dcd dsr cts ri
17 LTC1343 no-cable mode the no-cable mode (m0 = m1 = m2 = 1) is intended for the case when the cable is disconnected from the connector. the charge pump, bias circuitry, drivers and receivers are turned off, the driver outputs are forced into a high impedance state, and the supply current drops to less than 200 m a. it can also be used to share i/o lines with other drivers and receivers without loading down the signals. charge pump the LTC1343 uses an internal capacitive charge pump to generate v dd and v ee as shown in figure 28. a voltage doubler generates about 8v on v dd and a voltage inverter generates about C 7.5v for v ee . four 1 m f surface mounted tantalum or ceramic capacitors are required for c1, c2, c3 and c4. the v ee capacitor c5 should be a minimum of 3.3 m f. all capacitors are 16v. receiver fail-safe and glitch filter all LTC1343 receivers feature fail-safe operation in all modes except no-cable mode. if the receiver inputs are left floating or shorted together by a termination resistor, the receiver output will always be forced to a logic high. external pull-up resistors are required on receiver outputs if fail-safe operation in the no-cable mode is desired. when the chip is configured for control signals by pulling the ctrl/clk pin high, a glitch filter is connected to all receiver inputs. the filter will reject any glitches at the receiver inputs less than 300ns. v.10 driver rise and fall times the rise and fall times of the v.10 drivers is programmed by placing a 1/8w, 5% resistor between the 423 set (pin 25) and ground. the graph of driver rise and fall times vs resistor value is shown in figure 29. enabling the single-ended driver and receiver when the LTC1343 is being used to generate the control signals (ctrl/clk = high) and the ec pin is pulled low, the dce/dte pin becomes an enable for driver 1 and receiver 4 so their inputs and outputs can be tied together as shown in figure 30. applicatio n s i n for m atio n wu u u figure 30. single-ended driver and receiver enable figure 29. v.10 driver rise and fall time vs resistor value figure 28. charge pump 44 43 42 41 40 1343 f28 1 2 3 4 8 c3 1 m f c4 1 m f 5v c1 1 m f c2 1 m f c5 3.3 m f LTC1343 v dd c1 + pwrv cc c1 v cc c2 + c2 v ee pgnd gnd + + + + + resistance ( ) driver rise/fall time ( m s) 1k 100 10 1 0.1 100k 1m 5m 1343 f29 10k 39 26 LTC1343 1343 f30 5 21 16 20 24 ec d1 ctrl/clk dce/dte r4 v cc
18 LTC1343 drivers and receivers into a high impedance state. in the dce mode, the middle two LTC1343s are enabled and the top and bottom LTC1343s disabled. with this scheme, any connector pin can be configured for sending or receiving signals. note that only one ltc1344 is required. multiprotocol interface with ring-indicate and a db-25 connector if the ri signal in rs232 mode is implemented, driver 4 and receiver 1 in the control chip can be tied to connector pin 22 in order to implement the ri signal in rs232 mode and dsr b signal for the other modes. figure 35 shows the dte configuration and figure 36 the dce configuration. in dce mode, the dce/dte pin should be driven with a logic signal from the controller that goes low only when the interface is in the rs232 mode. since the receiver 4 input impedance is greater than 30k w in all modes except rs232, it can be enabled at all other times and not load down the line. when driver 1 is disabled, it remains in a high impedance state and does not load the line. cable-selectable multiprotocol interface a cable-selectable multiprotocol dte/dce interface is shown in figure 37. the control signals ll, rl and tm are not implemented. the select lines m0, m1 and dce/dte are brought out to the connector. the mode is selected through the cable by wiring m0 (connector pin 18), m1 (connector pin 21) and dce/dte (connector pin 25) to ground (connector pin 7) or letting them float. if m0, m1 or dce/dte are floating, pull-up resistors r3, r4 and r5 will pull the signals to v cc . the select bit m1 is hard wired to v cc . when the cable is pulled out, the interface will go into the no-cable mode. multiprotocol interface with a m db-26 connector the controller-selectable multiprotocol dte/dce inter- face with a standard m db-26 connector is shown in figure 38. the rl, ll and tm signals are implemented and ri is mapped to pin 26 on the connector. a cable-selectable version is shown in figure 39. the tm and rl signals have been dropped, but ll is still implemented. the ec pin has no affect on the configuration when ctrl/ clk is high except to allow the dce/dte pin to become an enable. when dce/dte is low, the driver 1 output is enabled. the receiver 4 output goes into three-state and the input presents a 30k w load to ground. when dce/dte is high, the driver 1 output goes into three- state and the receiver 4 output is enabled. the receiver 4 input presents a 30k w load to ground in all modes except when configured for rs232 operation when the input impedance is 5k w to ground. dte vs dce operation the dce/dte pin does not allow a given LTC1343 pin to be reconfigured as a driver or receiver. the dce/dte pin only selects the loop-back topology and acts as an enable for the single-ended driver and receiver for control signals. however, the LTC1343 can be configured for either dte or dce operation in one of three ways: a dedicated dte or dce port with a connector of appropriate gender, a port with one connector that can be configured for dte or dce operation by rerouting the signals to the LTC1343 using a dedicated dte cable or dedicated dce cable, or a port with one connector and one cable using four LTC1343s. a dedicated dte port using a db-25 male connector is shown in figure 31. the interface mode is selected by logic outputs from the controller or from jumpers to either v cc or gnd on the mode select pins. a dedicated dce port using a db-25 female connector is shown in figure 32. a port with one db-25 connector that can be configured for either dte or dce operation is shown in figure 33. the configuration requires separate cables for proper signal routing in dte or dce operation. for example, in dte mode, the txd signal is routed to connector pins 2 and 14 via driver 2 in the LTC1343. in dce mode, driver 2 now routes the rxd signal to pins 2 and 14. a combination dte/dce port that doesnt require separate dce/dte cables is shown in figure 34. in dte mode, the top and bottom LTC1343s are enabled and the middle two are placed in the no-cable mode, which forces all of the applicatio n s i n for m atio n wu u u
19 LTC1343 figure 31: controller-selectable multiprotocol dte port with db-25 connector applicatio n s i n for m atio n wu u u LTC1343 1 2 4 3 8 5 6 7 9 10 39 38 37 36 35 34 33 32 31 30 29 28 27 26 21 19 18 17 12 13 14 15 16 40 23 20 22 11 25 ctrl latch invert 423 set dce m2 m1 m0 r2 r3 r4 r1 100k ll a (141) txd a (103) txd b scte a (113) scte b rxc a (115) rxc b rxd a (104) rxd b rts a (105) rts b dtr a (108) dtr b dcd a (109) dcd b dsr a (107) dsr b cts a (106) cts b tm a (142) 18 20 22 23 24 1 m0 m1 m2 dce/ dte 13 latch latch 21 12 11 38 c6 100pf c7 100pf 19 17 18 15 16 10 9 7 6 4 5 2 44 c2 1 m f c4 3.3 m f c10 1 m f c13 3.3 m f c5 1 m f c1 1 m f 43 42 41 14 v ee v cc v cc 5v 2 14 24 11 15 12 17 9 3 16 25 7 1 4 19 20 23 6 22 8 10 5 13 21 rl a (140) 1343 f31 db-25 male connector ltc1344 c8 100pf r1 c3 1 m f gnd lb v cc v cc v cc ec 24 LTC1343 1 2 4 3 8 5 6 7 9 10 39 38 37 36 35 34 33 32 31 30 29 28 27 26 21 19 18 17 24 12 13 14 15 16 40 23 20 22 11 25 ctrl latch invert 423 set dce m2 m1 m0 r2 r3 r4 r2 100k 44 c12 1 m f c9 1 m f 43 42 41 c11 1 m f gnd lb ec r1 ll txd scte txc rxc rxd tm rl rts dtr dcd dsr cts latch m2 m1 m0 sgnd (102) shield (101) charge pump charge pump d1 d2 d3 d4 d1 d2 d3 d4 txc a (114) txc b lb + + + + + + + + + +
20 LTC1343 applicatio n s i n for m atio n wu u u figure 32: controller-selectable multiprotocol dce port with db-25 connector LTC1343 1 2 4 3 8 5 6 7 9 10 39 38 37 36 35 34 33 32 31 30 29 28 27 26 21 19 18 17 12 13 14 15 16 40 23 20 22 11 25 ctrl latch invert 423 set dce m2 m1 m0 r2 r3 r4 r1 100k tm a (142) rxd a (104) rxd b rxc a (115) rxc b txc a (114) txc b scte a (113) scte b txd a (103) txd b ll a (141) cts a (106) cts b dsr a (107) dsr b dcd a (109) dcd b dtr a (108) dtr b rts a (105) rts b rl a (140) 25 20 22 23 24 1 m0 m1 m2 v cc dce/ dte 13 12 11 38 c6 100pf c7 100pf 19 17 18 15 16 10 9 7 6 4 5 2 44 c2 1 m f c4 3.3 m f c10 1 m f c13 3.3 m f c5 1 m f c1 1 m f 43 42 41 14 v ee v cc v cc 5v 3 16 17 9 15 12 24 11 2 14 18 7 1 5 13 8 10 6 22 20 23 4 19 21 1343 f32 db-25 female connector ltc1344 c8 100pf r1 c3 1 m f gnd lb v cc v cc v cc v cc v cc v cc v cc ec 24 LTC1343 1 2 4 3 8 5 6 7 9 10 39 38 37 36 35 34 33 32 31 30 29 28 27 26 21 19 18 17 12 13 14 15 16 40 23 20 22 11 25 dce m2 m1 m0 r2 r3 r4 r2 100k 44 c12 1 m f c9 1 m f 43 42 41 c11 1 m f gnd lb ec ctrl latch invert 423 set r1 tm rxd rxc txc scte txd ll cts dsr dcd dtr cts rl lb m2 m1 m0 latch sgnd (102) shield (101) charge pump charge pump d1 d2 d3 d4 d1 d2 d3 d4 24 + + + + + + + + + + latch latch 21
21 LTC1343 figure 33. controller-selectable multiprotocol dte/dce port with db-25 connector applicatio n s i n for m atio n wu u u LTC1343 1 2 4 3 8 5 6 7 9 10 39 38 37 36 35 34 33 32 31 30 29 28 27 26 21 19 18 17 12 13 14 15 16 40 23 20 22 11 25 ctrl latch invert 423 set dce m2 m1 m0 r2 r3 r4 r1 100k ll a txd a txd b scte a scte b tm a rxd a rxd b rxc a rxc b rxc a rxc b rxd a rxd b tm a rts a rts b dtr a dtr b dcd a dcd b dsr a dsr b cts a cts b dcd a dcd b dtr a dtr b rts a rts b 18 dte dce 20 22 23 24 1 m0 m1 m2 dce/ dte 13 12 11 38 c6 100pf c7 100pf 19 17 18 15 16 10 9 7 6 4 5 2 44 c2 1 m f c4 3.3 m f c10 1 m f c13 3.3 m f c5 1 m f c1 1 m f 43 42 41 14 v ee v cc v cc 5v 2 14 24 11 15 12 17 9 3 16 25 7 1 4 19 20 23 8 10 6 22 5 13 21 1343 f33 db-25 connector ltc1344 c8 100pf r1 c3 1 m f gnd lb v cc v cc v cc ec 24 LTC1343 1 2 4 3 8 5 6 7 9 10 39 38 37 36 35 34 33 32 31 30 29 28 27 26 21 19 18 17 12 13 14 15 16 40 23 20 22 11 25 ctrl latch invert 423 set dce m2 m1 m0 r2 r3 r4 r2 100k 44 c12 1 m f c9 1 m f 43 42 41 c11 1 m f gnd lb ec r1 dte_ll/dce_tm dte_txd/dce_rxd dte_scte/dec_rxc dte_txc/dce_txc dte_rxc/dce_scte dte_rxd/dce_txd dte_tm/dce_ll dte_rl/dce_rl dte_rts/dce_cts dte_dtr/dce_dsr dte_dcd/dce_dcd dte_dsr/dce_dtr dte_cts/dce_rts lb latch dce/dte m2 m1 m0 sgnd shield rl a cts a cts b dsr a dsr b rl a charge pump charge pump d1 d2 d3 d4 d1 d2 d3 d4 txc a txc b scte a scte b txd a txd b ll a txc a txc b 24 + + + + + + + + + + latch latch 21
22 LTC1343 figure 34. controller-selectable multiprotocol dte/dce port with db-25 applicatio n s i n for m atio n wu u u LTC1343 12 13 10 9 21 14 15 16 5 6 7 26 r2 r3 r4 tm a (142) rxd a (104) rxd b rxc a (115) rxc b txc a (114) txc b scte a (113) scte b txd a (103) txd b ll a (141) cts a (106) cts b dsr a (107) dsr b dcd a (109) dcd b dtr a (108) dtr b rts a (105) rts b rl a (140) 25 20 22 13 12 19 17 18 15 16 10 9 7 6 4 5 dce 39 38 37 36 35 34 33 28 29 30 32 31 27 3 16 17 9 15 12 24 11 2 14 18 7 5 13 6 22 8 10 20 23 4 19 21 1343 f34 db-25 connector ltc1344 dce/ dte dce/dte r1 sgnd (102) d1 d2 d3 d4 1 shield (101) LTC1343 12 13 10 9 21 14 15 16 5 cts dsr dcd dtr rts rl tm rxd rxc txc scte txd ll 6 7 v cc v cc 26 r2 r3 r4 dce 39 38 37 36 35 34 33 28 29 30 32 31 27 r1 d1 d2 d3 d4 LTC1343 12 13 10 9 21 14 15 16 5 6 7 26 r2 r3 r4 dce 39 38 37 36 35 34 33 28 29 30 32 31 27 r1 d1 d2 d3 d4 LTC1343 12 13 10 9 21 14 15 16 5 6 7 26 r2 r3 r4 dce 39 38 37 36 35 34 33 28 29 30 32 31 27 r1 d1 d2 d3 d4 11 38 c6 100pf c7 100pf c8 100pf
23 LTC1343 applicatio n s i n for m atio n wu u u figure 35. controller-selectable multiprotocol dte port with ri and db-25 connector LTC1343 1 2 4 3 8 5 6 7 9 10 39 38 37 36 35 34 33 32 31 30 29 28 27 26 21 19 18 17 12 13 14 15 16 40 23 20 22 11 25 ctrl latch invert 423 set dce m2 m1 m0 r2 r3 r4 r1 100k ll a (141) txd a (103) txd b scte a (113) scte b rxc a (115) rxc b rxd a (104) rxd b rts a (105) rts b dtr a (108) dtr b dcd a (109) dcd b dsr a (107) dsr b/ri a (125) cts a (106) cts b tm a (142) 18 20 22 23 24 1 m0 m1 m2 dce/ dte 13 12 11 38 c6 100pf c7 100pf 19 17 18 15 16 10 9 7 6 4 5 2 44 c2 1 m f c4 3.3 m f c10 1 m f c13 3.3 m f c5 1 m f c1 1 m f 43 42 41 14 v ee v cc v cc 5v 2 14 24 11 15 12 17 9 3 16 25 7 1 4 19 20 23 6 22 8 10 5 13 21 rl a (140) 1343 f35 db-25 male connector ltc1344 c8 100pf r1 c3 1 m f gnd lb v cc v cc v cc ec 24 LTC1343 1 2 4 3 8 5 6 7 9 10 39 38 37 36 35 34 33 32 31 30 29 28 27 26 19 18 17 12 13 14 15 16 40 23 20 22 11 25 ctrl latch invert 423 set m2 m1 m0 r2 r3 r4 r2 100k 44 c12 1 m f c9 1 m f 43 42 41 c11 1 m f gnd lb ec r1 ll txd scte txc rxc rxd tm rl rts dtr dcd dsr cts ri latch m2 m1 m0 sgnd (102) shield (101) charge pump charge pump d1 d2 d3 d4 d1 d2 d3 d4 txc a (114) txc b lb 24 v cc dce 21 + + + + + + + + + + latch latch 21
24 LTC1343 applicatio n s i n for m atio n wu u u figure 36. controller-selectable multiprotocol dce port with ri and db-25 connector LTC1343 1 2 4 3 8 5 6 7 9 10 39 38 37 36 35 34 33 32 31 30 29 28 27 26 21 19 18 17 12 13 14 15 16 40 23 20 22 11 25 ctrl latch invert 423 set dce m2 m1 m0 r2 r3 r4 r1 100k tm a (142) rxd a (104) rxd b rxc a (115) rxc b txc a (114) txc b scte a (113) scte b txd a (103) txd b ll a (141) cts a (106) cts b dsr a (107) dsr b/ri a (125) dcd a (109) dcd b dtr a (108) dtr b rts a (105) rts b rl a (140) 25 20 22 23 24 1 m0 m1 m2 v cc dce/ dte 13 12 11 38 c6 100pf c7 100pf 19 17 18 15 16 10 9 7 6 4 5 2 44 c2 1 m f c4 3.3 m f c10 1 m f c13 3.3 m f c5 1 m f c1 1 m f 43 42 41 14 v ee v cc v cc 5v 3 16 17 9 15 12 24 11 2 14 18 7 1 5 13 8 10 6 22 20 23 4 19 21 1343 f36 db-25 fema;e connector ltc1344 c8 100pf r1 c3 1 m f gnd lb v cc v cc v cc v cc v cc v cc ec 24 LTC1343 1 2 4 3 8 5 6 7 9 10 39 38 37 36 35 34 33 32 31 30 29 28 27 26 21 19 18 17 12 13 14 15 16 40 23 20 22 11 25 dce m2 m1 m0 r2 r3 r4 r2 100k 44 c12 1 m f c9 1 m f 43 42 41 c11 1 m f gnd lb ec ctrl latch invert 423 set r1 tm rxd rxc txc scte txd ll ri cts dsr dcd dtr ctx rl lb m2 m1 m0 latch sgnd (102) shield (101) charge pump charge pump d1 d2 d3 d4 d1 d2 d3 d4 rien = rs232 24 + + + + + + + + + + latch latch 21
25 LTC1343 applicatio n s i n for m atio n wu u u figure 37. cable-selectable multiprotocol dte/dce port with db-25 connector LTC1343 1 2 4 3 8 5 6 7 9 10 39 38 37 36 35 34 33 32 31 30 29 28 27 26 21 19 18 17 12 13 14 15 16 40 23 20 22 11 25 ctrl latch invert 423 set dce m2 m1 m0 r2 r3 r4 r1 100k txd a txd b scte a scte b rxd a rxd b rxc a rxc b rxc a rxc b rxd a rxd b rts a rts b dtr a dtr b dcd a dcd b dsr a dsr b cts a cts b dcd a dcd b dtr a dtr b rts a rts b dte dce 20 22 23 24 1 m0 m1 m2 dce/ dte 13 12 11 38 c6 100pf c7 100pf 19 17 18 15 16 10 9 7 6 4 5 2 44 c2 1 m f c4 3.3 m f c10 1 m f c13 3.3 m f c5 1 m f c1 1 m f 43 42 41 14 v ee v cc v cc 5v 2 14 24 11 15 12 17 9 3 16 7 1 4 19 20 23 8 10 6 22 5 13 25 21 18 1343 f37 db-25 connector ltc1344 c8 100pf r1 c3 1 m f gnd lb v cc v cc v cc v cc v cc v cc ec 24 LTC1343 1 2 4 3 8 5 6 7 9 10 39 38 37 36 35 34 33 32 31 30 29 28 27 26 21 19 18 17 12 13 14 15 16 40 23 20 22 11 25 ctrl latch invert 423 set dce m2 m1 m0 r2 r3 r4 r2 100k 44 c12 1 m f c9 1 m f 43 42 41 c11 1 m f gnd lb ec r1 dte_txd/dce_rxd dte_scte/dec_rxc dte_txc/dce_txc dte_rxc/dce_scte dte_rxd/dce_txd dte_rts/dce_cts dte_dtr/dce_dsr dte_dcd/dce_dcd dte_dsr/dce_dtr dte_cts/ dce_rts lb sgnd shield cts a cts b dsr a dsr b charge pump charge pump d1 d2 d3 d4 txc a txc b scte a scte b txd a txd b txc a txc b r5 10k r4 10k dce/dte m1 m0 v cc v cc d1 d2 d3 d4 24 r3 10k v cc cable wiring for mode selection mode pin 18 pin 21 v.35 pin 7 pin 7 eia-530, rs449, nc pin 7 v.36, x.21 rs232 pin 7 nc cable wiring for dte/dce selection mode pin 25 dte pin 7 dce nc + + + + + + + + + + latch 21
26 LTC1343 figure 38. controller-selectable multiprotocol dte/dce port with db-26 connector applicatio n s i n for m atio n wu u u LTC1343 1 2 4 3 8 5 6 7 9 10 39 38 37 36 35 34 33 32 31 30 29 28 27 26 21 19 18 17 12 13 14 15 16 40 23 20 22 11 25 ctrl latch invert 423 set dce m2 m1 m0 r2 r3 r4 r1 100k ll a txd a txd b scte a scte b tm a rxd a rxd b rxc a rxc b rxc a rxc b rxd a rxd b tm a rts a rts b dtr a dtr b dcd a dcd b dsr a dsr b cts a cts b ri a dcd a dcd b dtr a dtr b rts a rts b rl a 18 dte dce 20 22 23 24 1 m0 m1 m2 dce/ dte 13 12 11 38 c6 100pf c7 100pf 19 17 18 15 16 10 9 7 6 4 5 2 44 c2 1 m f c4 3.3 m f c10 1 m f c13 3.3 m f c5 1 m f c1 1 m f 43 42 41 14 v ee v cc v cc 5v 2 14 24 11 15 12 17 9 3 16 25 7 1 4 19 20 23 8 10 6 22 5 13 26 21 1343 f38 m db-26 connector ltc1344 c8 100pf r1 c3 1 m f gnd lb v cc v cc v cc v cc ec 24 LTC1343 1 2 4 3 8 5 6 7 9 10 39 38 37 36 35 34 33 32 31 30 29 28 27 26 21 19 18 17 12 13 14 15 16 40 23 20 22 11 25 ctrl latch invert 423 set dce m2 m1 m0 r2 r3 r4 r2 100k 44 c12 1 m f c9 1 m f 43 42 41 c11 1 m f gnd lb ec r1 dte_ll/dce_tm dte_txd/dce_rxd dte_scte/dec_rxc dte_txc/dce_txc dte_rxc/dce_scte dte_rxd/dce_txd dte_tm/dce_ll dte_rl/dce_ri dte_rts/dce_cts dte_dtr/dce_dsr dte_dcd/dce_dcd dte_dsr/dce_dtr dte_cts/dce_rts dte_ri/dce_rl lb latch dce/dte m2 m1 m0 sgnd shield rl a cts a cts b dsr a dsr b ri a charge pump charge pump d1 d2 d3 d4 d1 d2 d3 d4 txc a txc b txc a txc b 24 scte a scte b txd a txd b ll a + + + + + + + + + + latch latch 21
27 LTC1343 figure 39. cable-selectable multiprotocol dte port with db-26 connector applicatio n s i n for m atio n wu u u information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. LTC1343 1 2 4 3 8 5 6 7 9 10 39 38 37 36 35 34 33 32 31 30 29 28 27 26 21 19 18 17 12 13 14 15 16 40 23 20 22 11 25 ctrl latch invert 423 set dce m2 m1 m0 r2 r3 r4 r1 100k txd a txd b scte a scte b rxd a rxd b rxc a rxc b rxc a rxc b rxd a rxd b rts a rts b dtr a dtr b dcd a dcd b dsr a dsr b cts a cts b ll b dcd a dcd b dtr a dtr b rts a rts b ll b dte dce 20 22 23 24 1 m0 m1 m2 dce/ dte 13 12 11 38 c6 100pf c7 100pf 19 17 18 15 16 10 9 7 6 4 5 2 44 c2 1 m f c4 3.3 m f c10 1 m f c13 3.3 m f c5 1 m f c1 1 m f 43 42 41 14 v ee v cc v cc 5v 2 14 24 11 15 12 17 9 3 16 7 1 4 19 20 23 8 10 6 22 5 13 26 25 21 18 1343 f39 m db-26 connector ltc1344 c8 100pf r1 c3 1 m f gnd lb v cc v cc v cc v cc v cc v cc ec 24 LTC1343 1 2 4 3 8 5 6 7 9 10 39 38 37 36 35 34 33 32 31 30 29 28 27 26 21 19 18 17 12 13 14 15 16 40 23 20 22 11 25 ctrl latch invert 423 set dce m2 m1 m0 r2 r3 r4 r2 100k 44 c12 1 m f c9 1 m f 43 42 41 c11 1 m f gnd lb ec r1 dte_txd/dce_rxd dte_scte/dec_rxc dte_txc/dce_txc dte_rxc/dce_scte dte_rxd/dce_txd dte_rts/dce_cts dte_ll/dce_ll dte_dtr/dce_dsr dte_dcd/dce_dcd dte_dsr/dce_dtr dte_cts/dce_rts lb sgnd shield cts a cts b dsr a dsr b charge pump charge pump d1 d2 d3 d4 txc a txc b scte a scte b txd a txd b txc a txc b r5 10k r4 10k dce/dte m1 m0 v cc v cc d1 d2 d3 d4 24 r3 10k v cc cable wiring for mode selection mode pin 18 pin 21 v.35 pin 7 pin 7 eia-530, rs449, nc pin 7 v.36, x.21 rs232 pin 7 nc cable wiring for dte/dce selection mode pin 25 dte pin 7 dce nc + + + + + + + + + + latch 21
28 LTC1343 1343fa lt/tp 0899 2k rev a ? printed in usa ? linear technology corporation 1996 dimensions in inches (millimeters) unless otherwise noted. package descriptio n u gw package 44-lead plastic ssop (wide 0.300) (ltc dwg # 05-08-1642) related parts part number description comments ltc1321 dual rs232/rs485 transceiver 2 rs232 driver/receiver pairs or 2 rs485 driver/receiver pairs ltc1334 single 5v rs232/rs485 multiprotocol transceiver 2 rs232 driver/receiver or 4 rs232 driver/receiver pairs ltc1344/ltc1344a software-selectable cable terminator perfect for terminating the LTC1343 ltc1345 single supply v.35 transceiver 3 driver/3 receiver for data and clock signals ltc1346a dual supply v.35 transceiver 3 driver/3 receiver for data and clock signals ltc1543 software-selectable multiprotocol transceiver 3 driver/3 receiver for data and clock signals ltc1544 software-selectable multiprotocol transceiver 4 driver/4 receiver for control signals including ll ltc1545 software-selectable multiprotocol transceiver 5 driver/5 receiver for control signals including ll, rl, tm linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear-tech.com g44 ssop 1098 0 ?8 typ 0.231 ?0.3175 (0.0091 ?0.0125) 0.610 ?1.016 (0.024 ?0.040) 7.417 ?7.595** (0.292 ?0.299) 45 0.254 ?0.406 (0.010 ?0.016) 2.286 ?2.387 (0.090 ?0.094) 0.127 ?0.292 (0.005 ?0.0115) 2.463 ?2.641 (0.097 ?0.104) 0.800 (0.0315) bsc 0.304 ?0.431 (0.012 ?0.017) 17.805 ?18.059* (0.701 ?0.711) 123456789101112131415161718192021 10.160 ?10.414 (0.400 ?0.410) 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 dimension does not include mold flash. mold flash shall not exceed 0.152mm (0.006") per side note: dimensions are in millimeters * dimension does not include interlead flash. interlead flash shall not exceed 0.254mm (0.010") per side **

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